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Ethernovia

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Senior ASIC Design Verification Engineer

Ethernovia

Onsite

Posted: Sep 12, 2026

San Jose, CABe among the first 25 applicants

10+ years exp$200,000 - $300,000/year

Hardware & Semiconductors

Automotive

Verilog

SystemVerilog

UVM

Python

TCL

C/C++

+4 more

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San Jose Ca

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