Senior Asic Design Verification Engineer Jobs at Ethernovia

Market Insights for Senior Asic Design Verification Engineer in Ethernovia

Real-time data from 1 active listings in the last 30 days.

Active Roles

Avg. Salary

$250K

Top Hiring Locations

San Jose, CA

Senior ASIC Design Verification Engineer

Onsite

Posted: Sep 12, 2026

San Jose, CABe among the first 25 applicants

10+ years exp$200,000 - $300,000/year

Hardware & Semiconductors

Automotive

Verilog

SystemVerilog

UVM

Python

TCL

C/C++

+4 more

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