Ddr Memory Interface System Validation Lead Engineer Jobs at Altera

Market Insights for Ddr Memory Interface System Validation Lead Engineer in Altera

Real-time data from 1 active listings in the last 30 days.

Active Roles

Avg. Salary

$182K

Top Hiring Locations

San Jose, CA

DDR Memory Interface System Validation Lead Engineer

Onsite

Posted: Sep 3, 2026

San Jose, CA28 applicants

8+ years exp$149,100 - $215,000/yearFull Time

Hardware & Semiconductors

DDR5

LPDDR5

FPGA

PHY

protocol analyzers

oscilloscopes

+3 more

24/7 job-alert agent

Speed is everything. Get an instant alert the second a new Ddr Memory Interface System Validation Lead Engineer position is posted at Altera.

Instant Telegram alerts·7-day free trial·No credit card required